The scaling of gate dielectrics—also referred to as gate oxides—to smaller thickness is one of the key elements that enables the continued scaling of silicon complementary-metal-on-silicon (CMOS) technology to higher performance levels. Also, having multiple thicknesses for gate oxides (also called gate dielectrics) on a single integrated circuit (IC) chip is desirable to address power and performance concerns as well as input/output (I/O) circuit needs. The thin gate dielectrics are used for the high performance parts of the circuit design, however the thin gate dielectrics also have higher leakage, so they cannot be used on the entire chip. The thicker gate dielectrics are used for lower performance, non-critical devices, which reduces power dissipation by reducing gate leakage. Additionally, these thicker gate dielectric devices are needed to support I/O circuits that require high voltage operation. Thin gate dielectrics are generally unable to meet lifetime requirements at such high voltages.
Thinner gate dielectrics generate more inversion charge, and improve short-channel effects by increasing gate control of the channel. Because the gate dielectric is formed at the interface where the inversion layer is formed and transistor current is conducted, this bottom interface must be extremely high quality. As gate oxide thickness is reduced below 20 Angstroms, even the top interface with the poly (polysilicon; poly-Si) has increasing influence on the conduction in the channel region, so is also important to maintain the quality of the gate oxide/poly-Si interface. The relative importance of this top interface becomes more and more significant as the gate oxide is reduced in thickness.
Typical physical thickness of advanced silicon oxynitride gate dielectric is only 13 Angstroms for 5–7 Si—O bonds. It is known that the top gate dielectric interface (the interface between a gate dielectric and a gate electrode) affect the overall electrical property of such thin dielectrics. For instance, an exposure of the oxynitride surface to water (H2O) undesirably increases the dielectric thickness and replaces nitrogen atoms in the vicinity of the top interface with oxygen atoms undesirably reducing overall dielectric constant of the gate dielectric. In order to preserve such ultra thin gate dielectric, any exposure of gate dielectric to wet chemicals is avoided and the waiting time between processes of forming gate dielectric and depositing gate electrode is minimized. Preferably, the gate electrode is deposited immediately after form gate dielectric without breaking vacuum.
Dielectric materials with dielectric constant (k) higher than that of oxynitride are considered as a replacement to pure oxynitride gate dielectric. HfO2, HfSixOy, HfSixOyNz are the most promising candidates for the advanced high-k based gate dielectric. (The term “high-k” is used to describe a dielectric material featuring a dielectric constant k which is higher than 3.9 which is the k of SiO2.) A typical gate dielectric stack with high-k materials is composed of extremely thin silicon oxide, oxynitride, or nitride followed by a high-k material. It was found that the top surface of a typical high-k material reacts with the gate electrode producing a substantially large fixed electrical charge at the top interface. Electrical properties of the top interface unpredictably vary depending on a chemical state of the top high-k material surface. Subsequently, there is a need of preserving and controlling chemical state of the high-k interface.
U.S. Pat. No. 6,063,670 discloses gate fabrication processes for split-gate transistors. A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed therein. A circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first gate dielectric (20). The disposable layer (22) comprises a material that may be removed selectively with respect to silicon and the gate dielectric, such as germanium (Ge). If desired, a second dielectric layer (24) may be formed over the disposable layer (22). A pattern (26) is then formed exposing areas (14) of the circuit where a thinner gate dielectric is desired. The second dielectric layer (24), if it is present, and the disposable layer (22) are removed from the exposed areas. The pattern (26) is then removed. Following pre-gate cleaning, the second gate dielectric (30) is formed. The remaining portions of the disposable layer (22) may be removed either prior to, during, or after the second gate dielectric formation (30).
U.S. Pat. No. 6,140,185 (“Kimura”) discloses method of manufacturing semiconductor device. A first gate oxide film is formed on a surface of a silicon substrate. A first polycrystalline silicon film is formed on the first gate oxide film, and patterned so that its side surface is tapered. Silicon oxide film exposed through the first polycrystalline silicon is removed, and a second silicon oxide film having film thickness different from that of the first silicon oxide film is formed by thermal oxidation. Thus, dual gate oxide is manufactured.
FIGS. 14–17, Kimura shows forming a first gate oxide film 1a having a first portion on one side of a field oxide 2 and a second portion on an opposite side of the field oxide. The first portion of the first gate oxide is masked with photoresist (PR). Wet etching removes the second portion of first gate oxide. Then the photoresist is stripped, and thermal oxidation is performed again. This forms a new, second gate oxide in the second portion, and increases the thickness of the remaining first portion of the first gate oxide. Kirnura recognizes that photoresist in contact with the first gate oxide is not desirable, since is contains impurities. Kimura also recognizes that precleaning prior to growing the second gate oxide will also undesirably etch the first gate oxide.
In FIGS. 18–23, Kimura shows farming a first gate oxide film 1a having a first portion on one side of a field oxide and a second portion on an opposite side of the field oxide. A first polycrystalline silicon film doped with an impurity is formed on the entire surface, as a protective film for the first gate oxide film 1a. The first portion of the first gate oxide is masked with photoresist (PR). Then, the polysilicon over the second portion of the gate oxide is etched away. Then the photoresist is stripped, and thermal oxidation is performed again. This forms a new, second gate oxide in the second portion, and forms an oxide coating on the polysilicon over the first portion of the first gate oxide. In this embodiment, the entrance of Na impurities from the photoresist into the first gate oxide is prevented. Therefore, the first gate oxide film 1a is prevented from being rendered conductive, and variation of the threshold voltage of the MOS transistor is prevented.
In FIGS. 1–9, Kimura shows forming a first gate oxide film 1a having a first portion on one side of a field oxide 2 and a second portion on an opposite side of the field oxide. A first polycrystalline silicon film 4a doped with an impurity is formed on the entire surface, as a protective film for the first gate oxide film 1a. The first portion of the first gate oxide is masked with photoresist (PR) 5a. Then, the polysilicon over the second portion of the gate oxide is etched away. Then, the photoresist is stripped, and the first polycrystalline silicon film 4a is patterned and inclined to have an angle (tapered shape). Thereafter, the exposed second portion of the first gate oxide film is removed, and thermal oxidation is performed again. This forms a new, second gate oxide 1b in the second portion, and forms an oxide coating 6 on the polysilicon over the first portion of the first gate oxide. Condition of thermal oxidation is set such that the film thickness of the second gate oxide film 1b differs from the film thickness of the first gate oxide film 1a. Thus, dual gate oxide is formed.
FIGS. 1A–1C illustrate an exemplary prior art technique for forming multiple gate dielectrics (e.g., oxides) on a semiconductor substrate 102. A sequence of steps and structures resulting therefrom are illustrated. For purposes of this discussion, the substrate 102 has a top (as viewed) surface upon which semiconductor devices will be formed, and has two distinct areas (regions)—a left-hand (as viewed) area 102a and a right-hand (as viewed) area 102b. There can be many distinct areas on the semiconductor substrate. The semiconductor substrate 102 is suitably a semiconductor wafer.
First, the entire (both left- and right-hand areas) surface of the substrate 102 is prepared/precleaned, such as with ammonia hydroxide/hydrogen peroxide water mixture (APM, an example of which is “RCA”). Then, a thick dielectric (e.g., thick oxide) 104 is grown or deposited on the entire surface of the substrate 102. The thick dielectric 104 is suitably silicon dioxide (SiO2) or Silicon Oxynitride (SiON), and suitably has a thickness of approximately 2.0–5.5 nm (nanometers)=20–55 Angstroms. The thick dielectric 104 may be grown by thermal oxidation, or it may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like.
Then, photoresist (PR) 106 is applied and patterned, forming a soft mask for further processing steps, so that a first portion (left-hand side, as viewed) of the thick dielectric 104 is covered with photoresist 106 and a second portion (right-hand side, as viewed) of the thick dielectric 104 is exposed—i.e., it is not covered with photoresist 106. The resulting structure is shown in the cross-sectional view of FIG. 1A.
Next, the thick dielectric 104 is etched away in the exposed (not covered by photoresist) areas (portions), such as with hydrofluoric acid (HF) leaving the right-hand surface area of the substrate 102 exposed. And, the photoresist (soft mask) 106 is removed (stripped).
Then, the substrate is cleaned, again suitably using an RCA wet clean. The cleaning agent should not contain hydrofluoric acid (HF), because this would etch the desired remaining thick dielectric 104. And, a chemical oxide (chemical ox) 108 forms on the exposed (right-hand) area of the substrate 102. The chemical oxide 108 typically has a thickness of approximately 7–12 Angstroms. The resulting structure is shown in the cross-sectional view of FIG. 1B.
Next, a thin dielectric (e.g., thin oxide) 112 is grown or deposited over the entire surface of the substrate—i.e., over the exposed surface of the thick dielectric 104 and over the exposed surface of the chemical oxide 108. This can be done in the presence of a nitrogen plasma (N PLASMA) 110, so that the dielectric is silicon oxynitride (SiON). The thin dielectric (oxide) 112 suitably has a thickness of approximately 10–25 Angstroms. The thin dielectric 112 may be grown by a thermal process, or it may be deposited by a CVD or PVD process.
The resulting structure is shown in the cross-sectional view of FIG. 1C. In the resulting structure, the left-hand side 102a of the substrate 102 has thick dielectric (104+112), and the right-hand side 102b of the substrate 102 has thin dielectric (108+112).
The process described hereinabove can be repeated, multiple times, to achieve more than 2 different oxide thicknesses.
A number of disadvantages and problems are associated with the prior art process described hereinabove.                the process sequence must be thicker films (e.g., 104) first, then thinner films (e.g., 112);        the thick dielectric is exposed to the preclean for the thin dielectric;        the thick dielectric is exposed to thin gate dielectric growth or deposition process, and therefore:                    the tolerance on the thick oxide is degraded (exposed to multiple process); and            final dielectric properties of thick and thin dielectrics are coupled to each other.                        the thin dielectric area will have chemical oxide prior to growth, and HF cannot be used;        this sequence is not compatible with high-k integration. (If the high-k is deposited first, it will be exposed to the subsequent oxidation and may degrade as well as contaminate the tool. If the high-k is deposited second, it will be deposited in both areas.)        